Typically, copper (Cu) and Cu alloys are utilized as the thermal conductive substrate in silicon chips in high power device applications where junction temperature is limiting the device performance.
Carbon nanotubes (CNTs) are known for their ballistic electric and thermal transport properties. For example, the theoretical thermal conductivity of a single walled CNT is 6,000 Watt/((meter)(Kelvin)), while the thermal conductivity for a diamond is 2,000 W/((m)(K)). A single walled CNT has been measured in a lab to be 3,000 W/((m)(K)). A multi-walled CNT should have a higher thermal conductivity because the wall layers when the end cap is removed may act as parallel channels transporting more valence electron to increase conductivity.
Recently, researchers have demonstrated that by using lift-off processes, a patterned layer of catalyst can be formed on the substrate for the chemical vapor deposition (CVD) growth of well aligned multi-walled CNT arrays. Aligned CNTs grow readily from catalyst patterns into well defined vertical bundles. However the CNT bundles have poor adhesion to the substrate. Therefore, when CNT bundles reach more than 100 micrometers in length, they have difficulty in remaining upright. These difficulties have prevented the application of the CNT bundles, which have extremely high thermal conductivity, to macroscopic thermal management, such as silicon chip for high power device applications, in any meaningful way. Furthermore, a higher conductive substrate is needed to replace the conventional Cu and Cu alloys to produce desired silicon chips for high power device applications having improved thermal conductivity and having an improved coefficient of thermal expansion (CTE) silicon match.